A TFT-LCD (Thin-Film Transistor Liquid Crystal Display) includes a color filter substrate, an array substrate and a liquid crystal layer enclosed between the color filter substrate and the array substrate, the array substrate including a TFT. Taking a bottom-gate type TFT as an example, as shown in FIG. 1, the TFT of the array substrate generally includes a gate 10, a gate insulating layer (not shown in FIG. 1) being located on the gate 10 and completely covering the gate 10, an active layer 20 located on the gate insulating layer, an ohmic contact layer 30 located on the active layer 20, and a source 41 and a drain 42 both located on the ohmic contact layer 30, wherein the projection of the active layer 20 on the gate 10 is completely located within the gate 10, the source 41 and the drain 42 are partially overlapped with the active layer 20, and the ohmic contact layer 30 is located within a region where the source 41 and the drain 42 are overlapped with the active layer 20.
When a negative bias is applied to the gate 10 of the TFT to turn off the TFT, electrons in the active layer 20 of the TFT will flow to the gate insulating layer due to the negative bias on the gate. As a result, holes are formed in the active layer 20. Particularly, in the region where the active layer 20 is overlapped with the source 41 and the drain 42 of the TFT, the junction where the active layer 20 is intersected with the source 41 and the gate 10 (see region a in FIG. 1) and the junction where the active layer 20 is intersected with the drain 42 and the gate 10 (see region b in FIG. 1), a plurality of holes are formed. In the region where the active layer 20 is overlapped with the source 41 and the drain 42, an ohmic contact layer 30 is formed between the active layer 20 and the film layers of both the source 41 and the drain 42. As the electrons in the ohmic contact layer 30 may neutralize most holes, the number of the holes within the region where the active layer 20 is overlapped with the source 41 and the drain 42 will be reduced greatly. While at the junction where the active layer 20 is intersected with the source 41 and the gate 10 and the junction where the active layer 20 is intersected with the drain 42 and the gate 10, as the active layer 20 is in direct contact with the source 41 and the drain 42, the number of the holes will not be reduced greatly, a large gate negative bias leakage current is generated, and flicker is further caused. As a result, the problem of poor display quality occurs.
In conclusion, at present, a large gate negative bias leakage current will be generated at the junction where an active layer is intersected with and a source and a gate and at the junction where the active layer is intersected with a drain and the gate when a negative bias is applied to the gate, thereby resulting in the problem of poor display quality.